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Compact RISC-V Processor - 32 bit, 3-stage pipeline, 16 registers
The L11 is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and with 16 general purpose registers.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L10 and to generate corresponding hardware and software development kits.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L10 and to generate corresponding hardware and software development kits.
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Block Diagram of the Compact RISC-V Processor - 32 bit, 3-stage pipeline, 16 registers
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