768x39 Bits OTP (One-Time Programmable) IP, TSMC 55ULP 0.9V–1.2V / 2.5V
Coherent Network-on-chip (NoC) IP
C-NoC provides power control through power-islanding and a power-gating architecture at the interface port and router level, and is physically aware with automated insertion and deletion of pipelines to meet timing, generation of placement-aware groups and topologies, and power and frequency aware NoC generation.
C-NoC provides high performance with on-chip L3 cache support to reduce memory access latency, and its pipeline architecture provides scalability with maximum throughput and minimum latency. It is parity enabled to provide resiliency.
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