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Cognitive Radio IP Core
The Spectrum sensing core blindly detects occupied sub-carriers within a wide-band spectrum. The algorithm implemented in this core uses a patented algorithm (US 8,630,377 B2). The efficient real time implementation makes this core an ideal candidate to be used in cognitive radios. Spectrum sensing core is a fully parallel implementation which gives real time spectrum sensing capabilities allowing little to no interference to the incumbent. This spectrum sensing core is targeted to be used in radios developed based on IEEE802.22 standard.
This module is written in VHDL, capable of being used on any FPGA/ASIC architecture.
This module is written in VHDL, capable of being used on any FPGA/ASIC architecture.
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Block Diagram of the Cognitive Radio IP Core
