The CMAC1 core provides implementation of cryptographic hashes AES-CMAC per NIST SP 800-38B and AES-XCBC. The cores utilize “flow-through” design that can be easily included into the data path of a communication system or connected to a microprocessor: the core reads the data via the D input, key from the K input and outputs the hash result via its Q output. Data bus widths for D, K, and Q are parameterized. The design is fully synchronous and is available in both source and netlist form.
- Completely self-contained; does not require external memory
- CMAC algorithm per NIST SP800-38B and RFC 4493, AES-XCBC per CBC MAC submissions to NIST and RFC 3566.
- Supports 128, 192, and 256 bit AES keys.
- Flow-through design; flexible data bus width.
- Self-checking test bench provided
- Message digest calculation
Block Diagram of the CMAC and XCBC AES Core