CMAC and XCBC AES Core

The CMAC1 core provides implementation of cryptographic hashes AES-CMAC per NIST SP 800-38B and AES-XCBC. The cores utilize “flow-through” design that can be easily included into the data path of a communication system or connected to a microprocessor: the core reads the data via the D input, key from the K input and outputs the hash result via its Q output. Data bus widths for D, K, and Q are parameterized. The design is fully synchronous and is available in both source and netlist form.

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