Multi Protocol IO Concentrator (RDC) IP Core for Safe and Secure Ethernet Network
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Clocking Wizard
The Clocking Wizard is provided under the terms of the Xilinx End User License and is included with ISE and Vivado software at no additional charge.
The Clocking Wizard simplifies the process of configuring the clocking resources in Xilinx FPGAs.
The LogiCORE™ IP Clocking Wizard generates HDL source code to configure a clock circuit to user requirements. The wizard can either automatically select an appropriate clocking primitive and configure buffering, feedback, and timing parameters for a clocking network, or help the user configure the attributes for a manually selected primitive. If desired, the user may also override any wizard-calculated parameter. Besides generating source HDL for the clocking circuit, the wizard also invokes the Xilinx timing analysis tools to generate a timing parameter report.
The Clocking Wizard simplifies the process of configuring the clocking resources in Xilinx FPGAs.
The LogiCORE™ IP Clocking Wizard generates HDL source code to configure a clock circuit to user requirements. The wizard can either automatically select an appropriate clocking primitive and configure buffering, feedback, and timing parameters for a clocking network, or help the user configure the attributes for a manually selected primitive. If desired, the user may also override any wizard-calculated parameter. Besides generating source HDL for the clocking circuit, the wizard also invokes the Xilinx timing analysis tools to generate a timing parameter report.
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