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Clock-Reset Generator
特色
- up to 16 programmable dividers
- dividers can change ratio "on-the fly"
- each divider provides up to 16 gated clocks and 1 ungated
- PLL software control - restart for changing frequency, stop mode, bypass mode
- input reset sources - external hardware reset and up to 16 reset requests from other devices
- output reset signals - 1 non-programmable and up to 32 programmable
- APB slave interface with internal asynchronous bridge for registers programming
- static RTL configurable options - number of dividers, width of dividers counters, aligning of clocks from different dividers, number of gated clocks for each divider, and others
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