Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market
Clock generator, 180MHz~300MHz based PLL
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Phase Locked Loop PLL IP
- TSMC 12 FFC 4GHz Clock Generator / Clock Synthersizer, PLL (Fractional / Integer)
- TSMC 12 FFC 8GHz Clock Generator / Clock Synthersizer, PLL (Fractional / Integer)
- Phase Locked Loop (PLL) Frequency Synthesizer Core
- Phase Locked Loop (PLL) Module
- Phase Locked Loop (PLL) Macro
- 200 MHz—800 Mhz Phase Locked Loop IP Block