Clock/Data Recovery PLL
The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
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Block Diagram of the Clock/Data Recovery PLL
CDR IP
- SONET/SDH OC-3 / OC-12 Transceiver/CDR PHY
- Dual Band 25.78125G/28Gbps SerDes/CDR Available in TSMC 28nm 9LM HPC+
- Low jitter, low-power clock-deskew PLL operating from 6GHz to 9.5GHz
- 2.5 Gbps Transceiver core
- 4.25 Gbps Quad Multistandard SerDes
- Deserializer 1:32 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain