MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm)
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ChipScope Pro IBERT for Virtex-6 FPGA GTX Transceivers
The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTX transceivers can be used to evaluate and monitor GTX transceivers. The design includes pattern generators and checkers implemented in FPGA logic, and access to the ports and dynamic reconfiguration port (DRP) attributes of the GTX transceivers. Communication logic is also included to allow the design to be run-time accessible through JTAG. The IBERT core is a self-contained design. When generated, it will run through the entire implementation flow, including bit stream generation.
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Interface and Interconnect IP
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- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC