Digital Power Grid Overlay -- 20% to 40% Total Digital Dynamic Power Reduction
ChipScope Integrated Controller (ICON)
* Integrated Logic Analyzer (ILA)
* Virtual Input/Output (VIO)
* Agilent Trace Core 2 (ATC2)
Integrated Bus Analyzer (IBA) This interface allows the ChipScope Pro Analyzer software to communicate with these cores through the JTAG port of the device. The ICON core is designed to be easily instantiated and connected to these cores directly in a Verilog or VHDL design. The ICON core can also be added to an embedded processor system design using the Xilinx Embedded Development Kit (EDK) tools.
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Interface and Interconnect IP
- Standard Compliant AMBA AXI SoC Interconnect, Soft IP
- Standard Compliant AMBA AHB SoC Interconnect, Soft IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Serial Peripheral Interconnect Master & Slave Interface Controller
- Physical Layer Interface Core
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect