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Chip-to-Chip IO Buffer - TSMC CLN5
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-ended switching for efficient high-density utilization of available inter-chip routing tracks. It features core-voltage-level signal switching for low power and high voltage margin, and an unterminated receiver allowing for maximum signal swing at lowest power in ultra-short reach environments. The output is tristateable allowing for bi-directional signal flow.
The output driver is implemented in Analog Bits’ proprietary architecture that uses core devices only.
The output driver is implemented in Analog Bits’ proprietary architecture that uses core devices only.
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