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Capless 50mA LDO Regulator in 65nm
Low Drop Out Linear Regulator requiring no external discrete capacitor.
Very low on-chip area to allow lowest possible overall BOM cost.
Suitable for either Analog or Digital Loads.
Very low on-chip area to allow lowest possible overall BOM cost.
Suitable for either Analog or Digital Loads.
特色
- 65nm TSMC Logic LP Process, 6 Metals Used
- No Analog Process Options
- 1.4V – 3.3V Input Voltage
- 1.1V – 3.0V ±3% Output Voltage
- 50mA Load Current
- 250mV Drop Out Voltage
- Ground Current: 75uA
- Leakage Via Pass Device : 20nA
- Programmable Output Voltage in 100mV Steps
- Power Down Mode
- Scalable to load current and capacitance
优势
- Reduce total BOM cost
- Decrease BOM area footprint
- Enable power regulation in pad-limited designs
- Improved system reliability due to removed discrete
可交付内容
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (tlf)
- Behavioral Model (VHDL/Verilog)
- Integration Support
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Capless
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