CAN Bus Controller with Message Filter (Mailbox concept)
The CAN Bus Controller with Message Filter contains 32 receive buffers, each one with its own message filter, and 32 transmit buffers with prioritized arbitration scheme. For optimal support of Higher Layer Protocols (HLP) such as DeviceNet or SDC, the message filter covers the first two data bytes as well.
The design is written in technology independent HDL and can be mapped to ASIC and FPGA architectures and makes use of on-chip SRAM structures. An AMBA 3 Advanced Peripheral Bus (APB) interface enables smooth integration into ARM based SOC’s. This full synchronous bus interface can easily be connect to other system buses.
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