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Bit Block Transfer (BitBLT) Graphics Engine IP Core
The Bit Block Transfer (BitBLT) Graphics Engine IP Core provides hardware acceleration of block moves with Raster Operation (256 data manipulation operations) of off-screen or on-screen data within frame buffer memory in a graphic display system. In addition, the DB9100AXI4 provides hardware accelerated 2D graphics rendering capability. Utilizing the accelerated BitBLT & 2 D graphics operations, the DB9100AXI4 IP Core greatly increases software productivity.
The Bit Block Transfer (BitBLT) Graphics Engine IP Core works in parallel with the TFT LCD Controller IP Core, interfacing a microprocessor and frame buffer memory via the AMBA AXI4 Bus to a TFT LCD panel. Frame buffer memory typically is either on-chip SRAM memory or larger off-chip SRAM or SDRAM.
The Bit Block Transfer (BitBLT) Graphics Engine IP Core works in parallel with the TFT LCD Controller IP Core, interfacing a microprocessor and frame buffer memory via the AMBA AXI4 Bus to a TFT LCD panel. Frame buffer memory typically is either on-chip SRAM memory or larger off-chip SRAM or SDRAM.
特色
- Bit Block Transfer – 3 Independent Memory Sources of data:
- On-Screen & Off-Screen Data Block (SRC)
- Off-Screen Fixed Pattern Data Block (PTN)
- On-Screen visible Data Block (DST)
- 2D Raster Operations (ROP) performed on Block Transfers:
- 256 Raster Operations
- ROP0, ROP1, ROP2, & ROP3 operations
- Includes industries most popular 16 ROPs
- BitBLT Draw Features:
- Pixels, Horizontal & Vertical Lines
- Overlapping & Non-Overlapping Block Transfers
- Solid Color Block Fills
- FONT Monochrome Bitmap to Color Expansion, either Transparent or Opaque
- Rotation Block Transfers: 0, 90, 180, 270 degrees
- Block Stretch on X & Y Axis
- Alpha Blending
- Sprite Moves
- 2D Graphics Rendering Engine (Option):
- Pixel Drawing
- Line (Vector) Drawing – any direction
- Polygon Rendering
- Filled Polygon
- Command FIFO or Link-List Display Processing Unit
- Frame Buffer & Display Features Supported
- Display Resolutions 4K x 4K
- 8, 16 , 24, & 32 bits-per-pixel color depths
- Interrupt Controller with 3 sources of internal interrupts with masking control
- Reference Software Driver Included
- On-Chip Interconnect Compliance - AXI, AXI4, AHB, Avalon
- Compatible with Digital Blocks DB9000 Family of TFT LCD Controller IP Cores and Reference Designs
- Fully-synchronous, synthesizable Verilog RTL core
优势
- The DB9100 family of BitBLT Graphics Hardware Accelerator IP Cores provides a higher graphics performance than a Host or GPU, while offering higher software productivity.
可交付内容
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
Block Diagram of the BitBLT Graphics Hardware Accelerator (AXI4 Bus)
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