MIPI D-PHY 1.5Gbps (4-lanes TX/RX, PLL Integrated) TSMC 28HPM
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Bi-Directional LVDS with LVCMOS
BiDirectional LVDS IO circuit combines LVDS driver and receiver circuits to enable a single pair of IO pads to function as a 1.5Gbps bi-directional LVDS driver and receiver. Both driver and receiver circuits can be independently enabled (allowing driver, receiver, or loopback functions). If both driver and receiver circuits are disabled the IO pads function as independent single-ended LVCMOS IOs. The circuit has low area and power and operates o of standard IO and core supply voltages.
特色
- Compliant with TIA/EIA-644 LVDS standard, also meets sub-LVDS
- Receiver compatible with HSCL levels for differential clock/data input
- LVDS transmitter and receiver have independent power control
- LVDS transmitter has adjustable output current level
- Operation frequency up to 750MHz (1.5Gbps DDR)
- Operates with 2.5V or 3.3V IO supply
- Supports LVDS/LVCMOS operation
- On-chip 100 ohm termination resistor can be turned off and trimmed
- Uses on-chip bandgap input reference voltage
- LVCMOS output at 12mA, up to 125MHz
- LVCMOS input with hysteresis up to 125MHz
可交付内容
- GDSII
- CDL Netlist (MG Calibre Compatible)
- Functional Verilog Model
- Liberty timing models (.lib)
- LEF
- Application Note with integration and production test guidelines
Block Diagram of the Bi-Directional LVDS with LVCMOS
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