Bi-directional High speed interface lane up to 12.5Gbps
The total architecture is highly integrable and can be adapted to the customer’s requirements easily. The small area (0.1 sq mm) and low power consumption per lane are the key features of it which can lead to increased data transfer by simply combining more physical lanes.
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serdes IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Low-Latency SerDes PMA
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency