NVM OTP in GF (180nm, 130nm, 65nm, 55nm, 40nm, 28nm, 22nm, 12nm)
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BCH Error Correcting Code ECC
BCH code statistics for different `$mm` `$tt`
Zero latency, low gate count, low power, asynchronous BCH Code based Error Correction FEC:
The whole operation of encoding and decoding is asynchronous and is pure combinatorial gates without use of any synchronous logic, making it zero latency RTL.
Symbol Size is 1 bit and variables are ‘m’ bits wide for Galois Field operations.
Zero latency, low gate count, low power, asynchronous BCH Code based Error Correction FEC:
The whole operation of encoding and decoding is asynchronous and is pure combinatorial gates without use of any synchronous logic, making it zero latency RTL.
Symbol Size is 1 bit and variables are ‘m’ bits wide for Galois Field operations.
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Block Diagram of the BCH Error Correcting Code ECC
