32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
Baseline HDTV 1080p H.264/AVC Encoder Core
The core accepts up to the highest resolution HDTV video stream as input and outputs the encoded bitstream.
Simple, fully synchronous design with low gate count.
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H264 video AVC h.264 IP
- Multi-format decoder for 4K UHD with a single-core, 4:2:0 10-bit (max 8K). HEVC/H.265, AVC/H.264, VP9, AV1 and AVS2
- AV1/HEVC/AVC Single-core Encoder Video IP
- HEVC/AVC Dual-core Video Encoder HW IP
- H.264 Audio & Video Decoder IP
- Enhanced Multi-Format Encoder Supporting AV1
- Up To 5 MPixel Multi-Format Encoder