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AXI4-Stream Accelerator Adapter
The AXI4-Stream Accelerator Adapter is a soft Xilinx® LogiCORE™ Intellectual Property (IP) core used as a infrastructure block for connecting hardware accelerators to embedded CPUs.
It provides the AXI4-Stream interface to AXI4 infrastructure components and BRAM/FIFO interface towards Accelerator IP. This IP is used to improve the overall system-level performance for hardware accelerator IP in the FPGA logic.
It provides the AXI4-Stream interface to AXI4 infrastructure components and BRAM/FIFO interface towards Accelerator IP. This IP is used to improve the overall system-level performance for hardware accelerator IP in the FPGA logic.
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Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC