The AMBA AXI4 Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The AMBA AXI protocol supports high-performance, high-frequency system designs.
- AXI protocol compliant can be configured to support AXI4, AXI3 and AXI4-Lite protocols on all maser or slave ports, and additionally the AHB-Lite protocol on master ports.
- The AXI4 Interconnect core breaks-up burst transactions of more than 16 data beats from AXI4 masters into multiple transactions of no more than 16 beats when addressed to an AXI3 slave.
- Interface data widths:
- AXI4 / AXI3 / AHB-Lite : 32, 64, 128, 256 or 512 bits
- AXI4-Lite: 32 or 64 bits
- Support for Read-only and Write-only masters and slaves, resulting in reduced resource utilization.
- Address/ User width: Up to 64 bits
- Support for up to 8 masters and 32 slaves