The CoreAXItoAHBL is an AXI slave and an AHBLite master that provides an interface (bridge) between the AXI domain and AHB domain. The CoreAXItoAHBL allows an AXI bus system to be connected to an AHBLite bus.The AXI to AHBLite Bridge enables the AXI master to communicate with AHB slave. It allows the AXI bus to initiate data transfer between the two buses. The AXI slave interface and AHBLite master interface allows the AXI bus and AHB bus to access the read/write buffer memory.
- Provides an interface (bridge) between the AXI domain and AHB domain
- Makes alternate AXI write transaction and AXI read transactions possible
- Supports AXI data bus width of 64-bits, maximum burst size upto 8 bytes and maximum number of beats/transfer of 16
- Supports AHB data bus width of 32-bits
- Provides ERROR/OKAY response for every AXI master transaction
- Provides output signal to indicate whether the incoming AXI read/write address is aligned or unaligned address