The Quad Serial Peripheral Interface module either controls a serial data link as a master, or reacts to a serial data link as a slave.
The IPC-QSPI-AXI bus controller can be configured under software control to be a master or slave device. Reading and writing the core is done on the AMBA® AXI bus interface. The core operates in various data modes from 4-bits to 32-bits (8 modes are supported in multiples of 4 data bits). The data is then serialized and then transmitted, either LSB or MSB first, using the standard 4-wire SPI bus interface or the extended Dual or Quad Bus modes.
The IPC-QSPI-AXI module is compatible with various industry-standard DMA controllers. DMA operation in the IPC-QSPI-AXI can be enabled to assist a DMA controller in the loading (writing) of the transmit FIFO, and the unloading (reading) of the receive FIFO.
The Execute in Place (XIP) Mode allows an AXI Master to directly read the contents of any of several industry-standard FLASH devices (such as Winbond, Macronix, Spansion and Micron devices) simply by reading from the address space of the QSPI Controller.
The IPC-QSPI-AXI can be used with up to four SPI slave devices.
- Compatible with many industry-standard serial FLASH devices
- Execute-in-place (XIP)
- AMBA AXI4 interface
- DMA Interface
- Master or Slave mode
- Single, Dual and Quad-bit modes
- 4-bit to 32-bit serial TX / RX
- Full duplex operation
- Half duplex operation support
- Separate SCLK input for Master Mode
- 8 to 256 word TX / RX FIFO - configurable
- Asynchronous Slave Interface
- Interrupt control
- LSB or MSB mode
- Up to 4 slaves under Master control
- Motorola Serial Peripheral Interface (SPI) format support
- TI Synchronous Serial Frame format support
- National Microwire Frame format support
- Verilog Source
- Complete Verilog Test Environment
- C-Sample Code
Block Diagram of the AXI QSPI with Execute in Place