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AXI Performance Subsystem
The AXI Performance Subsystem is an AMBA® AXI4 based system that is useful as the digital infrastructure for building SOCs needing high performance. This system contains an 8 master, 16 slave AXI4 multi-matrix for supporting multiple high speed user AXI masters while providing high performance with Cortex-A5 class processors.
Additionally, the subsystem includes two DMA controllers for easily moving data from user peripherals to the “interleaved” internal SRAM controller for the highest contiguous SRAM performance possible.
Closely coupled Instruction and Data SRAM are available to the CPU as independent AXI multi-matrix slaves with high priority.
The AXI Performance Subsystem includes a standard set of peripherals and cores that supports RTOS and software kernels. Included is a QSPI, serial flash controller for boot loading program images or operating as an Execute in Place (XIP) engine using non-volatile external flash memory with low power.
The AXI Performance Subsystem is soft IP that can be used in all the popular semiconductor technology nodes.
Additionally, the subsystem includes two DMA controllers for easily moving data from user peripherals to the “interleaved” internal SRAM controller for the highest contiguous SRAM performance possible.
Closely coupled Instruction and Data SRAM are available to the CPU as independent AXI multi-matrix slaves with high priority.
The AXI Performance Subsystem includes a standard set of peripherals and cores that supports RTOS and software kernels. Included is a QSPI, serial flash controller for boot loading program images or operating as an Execute in Place (XIP) engine using non-volatile external flash memory with low power.
The AXI Performance Subsystem is soft IP that can be used in all the popular semiconductor technology nodes.
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Block Diagram of the AXI Performance Subsystem
