AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
The DB-SPI-FLASH-CTRL contains an AHB Slave Interconnect allowing for Memory Read of Flash Memory via the SPI Master Bus, and an AHB-Lite, AHB, or APB Slave Interface for Processor Configuration and Memory Read/Write of Flash Memory.
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