Scalable multicore architecture for a range of macrocells, small cells, cloud-RAN, DFE/DPD/ and more
Automotive MIPI A-PHY Source IP - 1-Lane
PHY IP supports the SOURCE function of MIPI A-PHY Gear-2 stated in standard specification. It supports data rate up to 4Gbps with integrated mixed signal circuit, high performance TX driver, embedded TX clock generation, on chip optional termination resistor calibration.
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Block Diagram of the Automotive MIPI A-PHY Source IP - 1-Lane

MIPI IP
- MIPI M-PHY in TSMC (28nm, 16nm, 12nm(
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
- Globalfoundries 12nm MIPI D-PHY V1.2@2.5GHz
- MIPI I3C Controllers - Dual Role Master (70016); APB I3C Slave (70002), Generic I3C Slave