Shader architecture type 3D GPU Integrating the OpenVG 1.1 hardware processing pipeline
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Audio ADDA IP, 24 bits, 96KHz, UMC 40nm LP process
24-Bit 96KHz Audio Codec, UMC 40nm Logic LP/HVT 2.5OD3.3 process.
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ADC/DAC IP
- 12bit 5Gsps silicon proven High performance Current Steering DAC IP Core
- Audio codec with capacitor-less 106 dB dynamic range ADC and 120 dB SNR DAC with low latency
- 12-bit 12-Gsps Transceiver (ADC/DAC/PLL)
- 8-bit 48-Gsps Transceiver (ADC/DAC/DLL)
- UCIe based 12-bit 12-Gsps Transceiver (ADC/DAC/PLL/UCIe)
- UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)