Aliathon’s ATM Framer Core provides a flexible, resource-efficient, high-density programmable logic based solution for ATM interfacing. Running at 155MHz, it is capable of processing thousands of ATM channels.
- Conforms to ITU I.432.1.
- Best-in-Class size and performance. Supports many thousands of channels.
- Multiple FPGA vendor support.
- Processes data for multiple independent TDM ATM streams.
- Configurable IDLE and Unassigned Cell insertion, detection and deletion.
- Optional HEC insertion; HEC error detection and correction.
- Supports multiple stream processing for glueless interfacing in multi-channel PDH systems.
- Supports dynamically ranged streams between 1 and 8 bits wide.
- Byte wide interface allows easy interface to Aliathon’s OC3/STM1, OC12/STM4 and 2xOC12/STM4 channelized systems.
- Configuration may be applied to each stream independently, and changed dynamically.
- Full Overhead and Defect processing per channel including:
- LCD, Uncorrectable HEC, Correctable HEC, Good HEC, IDLE detected.
- Performance Monitoring counters (Uncorrectable HEC, Correctable HEC, Good HEC).