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Asynchronous FIFO with flags and depth counter
特色
- Configurable for width and depth
- Configurable for fallthrough
可交付内容
- verilog RTL and Testbench
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Asynchronous FIFO IP
- Asynchronous FIFO alternate design
- USB 2.0 Device, Software Enumeration FIFO Interface (USB20SF)
- Expanded UART with FIFO, hard and soft flow control, synchronous mode
- UART : Universal Asynchronous Receiver Transmitter Core
- DO-254 FIFO Generator 1.00a
- Synchronous Universal Asynchronous Receiver/Transmitter