MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm) for Automotive
ASIP-1
查看 ASIP-1 详细介绍:
- 查看 ASIP-1 完整数据手册
- 联系 ASIP-1 供应商
Block Diagram of the ASIP-1
Programmable IP
- 512x8 Bits OTP (One-Time Programmable) IP, 12FFC 0.8V/1.8V
- Deep Neural Network Programmable Accelerator
- ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications
- 4Kx8 Bits OTP (One-Time Programmable) IP, 22nm FDX 0.8V/1.8V
- 1x64 Bits OTP (One-Time Programmable) IP, GlobalFoundries 22nm FDX 0.8V/1.8V
- 8Kx8 Bits OTP (One-Time Programmable) IP, VIS 0.15µm 1.8V/5V BCD GIII