MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
ASIL B Ready PCIe 5.0 Integrity and Data Encryption (IDE) Security IP
The Synopsys Integrity and Data Encryption (IDE) Security IP Module for PCIe
5.0 provides confidentiality, integrity, and replay protection for Transaction Layer Packets (TLP) over PCI Express interfaces as defined in the PCI-SIG IDE specification. The security module integrates seamlessly with the Synopsys PCIe 5.0 controllers to accelerate SoC integration.
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PCIE IP
- PCIe 5.0 Integrity and Data Encryption Security Module
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- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Multi-protocol SerDes PMA
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
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