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Arm Cortex-M0+
The Cortex-M0+ processor builds on the very successful Cortex-M0 processor, retaining full instruction set and tool compatibility, while further reducing energy consumption and increasing performance. Along with the Cortex-M0 processor, the exceptionally small silicon area, low power and minimal code footprint of these processors enable developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The Cortex-M0+ processor comes with a wide selection of options to provide flexible development.
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Block Diagram of the Arm Cortex-M0+
Arm IP
- LC3 / LC3plus Bluetooth LE Audio Codecs for Arm Cortex M55
- LC3 / LC3plus Bluetooth LE Audio Codecs for Arm Cortex M4 & M33
- ARM HSSTP PHY with Link Layer
- SPI Master / Slave Controller w/FIFO (APB Bus)
- eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)
- SPI Slave Controller (SPI2APB, SPI2AXI, SPI2AHB Bus)