Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger
You are here:
ARIA Crypto Accelerator
The EIP-11 ARIA algorithm, as specified in RFC 5794. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling and GHASH. Besides the basic feedback modes such as CBC, CFB, OFB, and CTR, the EIP-11 also provides CCM, CMAC, GCM, XTS, f8 and f9.
Designed for fast integration, low gate count, and maximum performance, the ARIA Engine provide a reliable and cost-effective ARIA IP solution that is easy to integrate into SoC designs.
Designed for fast integration, low gate count, and maximum performance, the ARIA Engine provide a reliable and cost-effective ARIA IP solution that is easy to integrate into SoC designs.
查看 ARIA Crypto Accelerator 详细介绍：
- 查看 ARIA Crypto Accelerator 完整数据手册
- 联系 ARIA Crypto Accelerator 供应商