ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications
The ARC-V RHX-100 processors are based on the RISC-V instruction set architecture (ISA). The processors feature a 34-bit physical address
space defined by the RISC-V Sv32 MMU. For applications requiring higher performance, the multi-core RHX-105 and RHX-105V are available with up to 16 CPU cores and up to 16 hardware accelerators in the processor cluster. RISC-V vector extensions (RVV) are available in the RHX-100V (single core) and RHX-105V (multi-core) processors.
The ARC-V RHX-100 features level 1 (L1) instruction and data cache and close coupled memory (CCM) and is optimized for use in high-performance real-time embedded applications.
查看 ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications 详细介绍:
- 查看 ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications 完整数据手册
- 联系 ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications 供应商
32-bit RISC-V processor IP
- RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
- ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
- 32-bit Embedded RISC-V Functional Safety Processor
- InCore Calcite Series: 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.