The DesignWare ARC HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety processors simplify development of high-performance safety-critical applications and accelerates ISO 26262 certification of automotive system-on-chips (SoCs). The ASIL D Ready processors feature a pre-verified dual-core lockstep implementation including a self -checking safety monitor. There is also an option to run the cores in performance mode for ASIL B or non-automotive applications requiring higher performance based on the same design.
Within the processors the interrupt controller, watchdog timer, and options such as cluster DMA and FPU are tightly coupled to the core and are instantiated within the main and shadow core for full redundancy.
The ARC HS Functional Safety processors are supported with comprehensive safety documentation including FMEDA reports and the ARC MetaWare Toolkit for Safety with ASIL D Ready certified compiler to generate ISO 26262 compliant code.
- High-speed, dual-issue, 10-stage pipeline
- Up to 16 MB instruction and data close coupled memory (CCM)
- 4 KB to 64 KB L1 instruction and data cache
- 64-bit loads and stores
- Register file supports 2 write ports and 2 read ports, and up to 8 contexts
- 32x32 multiplier
- Up to 240 interrupts, with up to 16 configurable preemption levels
- Native Arm® AMBA® AXI™ interface
- JTAG and Compact JTAG (cJTAG) debug interface
- Integrated, pre-verified hardware and software IP subsystem
- ARC EM processors with cache and DSP extensions deliver extremely low gate count and highly efficient processing performance
- Extensive library of software DSP functions enable sensor signal processing
- Hardware accelerators boost performance efficiency and reduce power consumption
- Integrated peripherals provide a wide range of SoC connectivity options for SoC/MCUs
- Options supporting higher performance voice/speech and sensor requirements
- V2V, V2x networks
- Vision controllers
- Automotive storage