The Veriest AMBA AXI Performance Monitor Design IP provides a mechanism for analysis of embedded AMBA AXI fabric latency. This gives added visibility to the software in order to debug performance related issues in an SoC in simulation or on a fabricated chip. There is a configurable number of AXI interfaces than can be monitored. The statistics are collected in counters which are visible to the embedded CPU over an APB interface. The channels that are monitored are the write write address, write data, read address and read data.