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AMBA AXI Data Prefetch Buffer
The Veriest AMBA AXI Data Prefetch Buffer Design IP provides a mechanism read / prefetch contiguous data over the AXI from a memory such as DDR SDRAM in which the data may need to be available immediately. The prefetched data is stored in a FIFO. The parameters for the source addresses are configured by way of the APB bus.
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Block Diagram of the AMBA AXI Data Prefetch Buffer
amba IP
- xSPI Master IP | NOR IP
- xSPI - PSRAM Master
- PCIe 5.0 Controller with AMBA AXI interface
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect