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AHB Lite to SPI Bridge
The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface. A custom 32-bit protocol is implemented on the SPI bus.
The AHB-Lite to SPI Bridge has two AHB-Lite Slave interfaces; one for access to the control/status registers (Register Interface), and another for access to the external SPI device (External Interface). The Bridge also has a SPI interface that operates exclusively as a SPI Master device.
The AHB-Lite to SPI Bridge has two AHB-Lite Slave interfaces; one for access to the control/status registers (Register Interface), and another for access to the external SPI device (External Interface). The Bridge also has a SPI interface that operates exclusively as a SPI Master device.
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Block Diagram of the AHB Lite to SPI Bridge
Bridge IP
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe Gen3 to SRIO Gen3 Bridge (FPGA)
- General Purpose & Bridge DMA
- RapidIO to AXI Bridge (RAB)
- Digital Capacitive Plus Bridge Sensor Interfaces