LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
AES IP Core
Countermeasures against side-channel attacks are implemented in the AES IP Core. Procenne AES IP Core is compatible with Xilinx FPGAs and INTEL FPGAs. VHDL is used as the Hardware Description Language of the IP Core. ECB, CBC, CTR, and GCM mode of operations are supported and implemented according to "NIST SP800-38a" and "NIST SP800-38d".
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Block Diagram of the AES IP Core
AES IP
- Secure-IC Securyzr™ Tunable Cryptography solutions with embedded side-channel protections: AES - SHA2 - SHA3 - PKC - RSA - ECC - Crystals Kyber - Crystals Dilithium - XMSS - LMS - SM2 - SM3 - SM4 - Whirlpool - CHACHA20 - Poly1305
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