Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
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AES IP Core
Encryption and Decryption are fed with an input of 128 bits length and an initial key of one of the supported key lengths (128, 192 and 256).
The AES IP Core is fully verified against “The advanced encryption standard algorithm validation suite (AESAVS)”.
The implementation of the AES IP Core exhibits very low latency, high speed, and low gate count with a simple interface for easy integration within SoC applications.
The AES IP Core is fully verified against “The advanced encryption standard algorithm validation suite (AESAVS)”.
The implementation of the AES IP Core exhibits very low latency, high speed, and low gate count with a simple interface for easy integration within SoC applications.
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Encryption IP
- PCIe 5.0 Integrity and Data Encryption Security Module
- CXL 2.0 Integrity and Data Encryption Security Module
- PCIe 6.0 Integrity and Data Encryption Security Module
- Inline Memory Encryption (IME) Security Module for DDR/LPDDR
- CXL 3.0 Integrity and Data Encryption Security Module
- UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8