55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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AES GCM IP Core
AES GCM IP Core is a Secure Symmetric Block Cipher IP Core that has compliance with the Advanced Encryption Standard (AES) specification in "FIPS 197". This standard specifies the Rijndael algorithm, a symmetric block cipher that can process data blocks of 128 bits, using cipher keys with lengths of 128, 192, and 256 bits.
Countermeasures against side-channel attacks (DPA) are implemented in the AES IP Core. AES GCM IP Core is compatible with Xilinx FPGAs and INTEL FPGAs. VHDL is used as the Hardware Description Language of the IP Core. GCM mode of operations is supported and implemented according to "NIST SP800-38a" and "NIST SP800-38d".
Countermeasures against side-channel attacks (DPA) are implemented in the AES IP Core. AES GCM IP Core is compatible with Xilinx FPGAs and INTEL FPGAs. VHDL is used as the Hardware Description Language of the IP Core. GCM mode of operations is supported and implemented according to "NIST SP800-38a" and "NIST SP800-38d".
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Block Diagram of the AES GCM IP Core
AES IP
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