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AES Engine IP (silicon proven)
YEESTOR's AES engine (ESAES) IP is a high-performance cryptographic engine operates in AES (Rijndael) NIST Federal information processing standard FIPS-197. It supports AES-ECB AES-XTS mode and 128/256 key-length both encryption/decryption. The core engine supports 128/256/512 data width operation. The encryption and decryption engines are-full duplex to provide high performance and support on-the-fly key update. ESAES is delivered with complete development package for the ease of use in both FPGA and SoC design.
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Block Diagram of the AES Engine IP (silicon proven)
AES IP
- UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
- FortiCrypt AES SX Series IP Core
- Tunable AES (ECB, CBC, CTR, XTS, CCM, GCM) accelerator - optional SCA protection
- AES-ECB-CBC-CFB-OFB-CTR-GCM-XTS-CCM Crypto Accelerator
- DPA Resistant AES Core
- AES + SHA DMA Crypto Accelerator