The IntelliProp IPC-BL204A-ZM is an AES-CTR (Counter Mode) Encryption Core supporting 128 or 256 bit encryption. The IPC-BL204A-ZM provides encryption/decryption based on a design principle known as substitution-permutation network (SP-network). An SP-network takes a block of the plaintext (clear data or non-encrypted data) and the key as inputs, and applies several alternating “rounds” or “layers” of substitution boxes and permutation boxes to produce the ciphertext (encrypted data). Counter Mode (CTR) is an extension upon the IntelliProp AES-ECB symmetric-key block-cipher to create a stream cipher that provides data confidentiality.
The IPC-BL204A-ZM is fully verified in pseudo random simulation. It is also compatible with OpenSSL’s AES-256-CTR cipher mode.
- • Full Verilog core
- • Synth-time selectable number of parallel paths allows the user to balance area/bandwidth requirements
- • Synth-time selectable internal buffer sizing for area/bandwidth balancing
- • Synth-time selectable 128 or 256 bit AES encryption key size
- • Optional internal Hamming ECC protection/correction on internal memories
- • Multiple independent data streams for flexible run-time dynamic packet sizing
- • Key expansion caching for optimized performance of packets using repeated keys
- • Packet queuing ready, for optimal throughput
- • Encrypted RTL code
- • Self-checking test bench in Verilog ModelSim (please contact IntelliProp for latest supported ModelSim versions). Other simulators may be supported, please check with IntelliProp.
- • Simulation scripts, vectors, and expected results.
- • Comprehensive user documentation.
- • Applications that require integration into the data path to provide encryption/decryption and authentication of data streams
- • Applications where high levels of encryption are required
- • Applications that require very high throughput and an encryption solution that has minimal impact on throughput
- • Applications that require a streaming data interface such as network traffic