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Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions
The Movellus™ high-performance Aeonic Generate Clock Generation Module (CGM) is a high-quality clock synthesis IP that is part of the Movellus Aeonic™ platform. Designed for high reliability and fully SCAN enabled, the CGM provides extensive visibility and controllability of key clocking metrics.
The CGM is constructed using Movellus’ patented TrueDigital™ technology. The product is delivered as soft IP and implemented using the customer’s standard cell library. With proven process portability (65 nm to 3 nm) and minimal area footprint, the CGM is ideally suited for large scale distribution within an SoC.
The CGM is constructed using Movellus’ patented TrueDigital™ technology. The product is delivered as soft IP and implemented using the customer’s standard cell library. With proven process portability (65 nm to 3 nm) and minimal area footprint, the CGM is ideally suited for large scale distribution within an SoC.
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