The SP1100-SP4000 is fully digital AWGN IP-Core that is scalable to up to 400Gb/s. It
generates white Gaussian noise, which can be used to perform BER Test to extremely
low BER levels (~10-15). The SP1100-SP4000 uses a combination of the Box-Muller algorithm
and the central limit theorem. The Box-Muller algorithm generates a unit normal random
variable via a transformation of two independent random variables that are uniformly
distributed. The outputs of multiple parallel Box-Muller designs are then averaged to
obtain a PDF that is Gaussian to up to 9σ.
The Additive White Gaussian Noise (AWGN) generator is widely used in BER Testing.
The software-based AWGN generator can take several days or several weeks for the BER
curve calculation when reach low bit error rates. Also, the transferring software generated
noise sample to the hardware IP is highly inefficient and it can be a performance
Hardware-based AWGN noise generator offers the speed of BER by several orders of
magnitude. It can be connected to the designed IP for BERT curve calculation in the
simulation. And also, it can be synthesized and implemented in FPGA with designed IP.
- Scalable from 10Gb/s to 400Gb/s @ 300MHz
- Probability desity function (PDF) deviation is in order of 10-4 and σ can reach 10.59
- Based on Box-Muller algorithm
- Period of generated noise sequence is ~ 2^88 = 10^25 samples
- SNR input selection is 16 bit covering from 0.0 dB to 15.9 dB
- Noise is quantized to 16 bits with 5 bits of integer and 11 bits of fraction
- Core returns to initial state upon reset
- Core can hold on and pause then continue the sequence when Enable pin is de-asserted
Block Diagram of the A Scalable 9σ Additive White Gaussian Noise (AWGN) Generator