USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
You are here:
A/D Converter IP, 24 bits, 96KHz, UMC 55nm SP process
24-Bit Stereo Analog-to-Digital converter with seperated digital audio interface, UMC 55nm SP/RVT Low-K Logic process.
查看 A/D Converter IP, 24 bits, 96KHz, UMC 55nm SP process 详细介绍：
- 查看 A/D Converter IP, 24 bits, 96KHz, UMC 55nm SP process 完整数据手册
- 联系 A/D Converter IP, 24 bits, 96KHz, UMC 55nm SP process 供应商
ADC/DAC IP
- Audio codec with capacitor-less 106 dB dynamic range ADC and 120 dB SNR DAC with low latency
- 12-bit 12-Gsps Transceiver (ADC/DAC/PLL)
- 8-bit 48-Gsps Transceiver (ADC/DAC/DLL)
- UCIe based 12-bit 12-Gsps Transceiver (ADC/DAC/PLL/UCIe)
- UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
- 16bit 5Msps SAR General Purpose ADC IP Core