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A 22nm Wirebond IO library with dynamically switchable 1.8V/3.3V GPIO, 3.3V I2C open-drain, & analog cells
A key attribute of the Certus 22nm IO library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation. The GPIO cell set can be configured as input, output, open-source, or open-drain with an optional internal 60K ohm pull-up or pull-down resistor. ESD cells for IO & core power & ground are constructed in an aggressive footprint. Digital cells for 25MHz, 75MHz, and 150MHz allow optimization across SSO currents & power. A 3.3V fail-safe I2C open-drain and 1.8V & 3.3V analog cells with ESD protection are also available. The library is enriched with feed-through, filler, transition and domain break cells to allow for flexible pad ring construction while maintaining ESD robustness.
Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we consistently exceed the standard ESD targets of 2KV HBM and 500V CDM, but we also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).
Certus supports IO libraries across multiple TSMC nodes including 180nm, 130nm, 40nm, 28nm, 22nm, and 16/12nm. Certus is particularly suited at providing custom variants in a cost-efficient framework. Please contact us for supplementary physical or electrical features that can suit your needs.
Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we consistently exceed the standard ESD targets of 2KV HBM and 500V CDM, but we also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).
Certus supports IO libraries across multiple TSMC nodes including 180nm, 130nm, 40nm, 28nm, 22nm, and 16/12nm. Certus is particularly suited at providing custom variants in a cost-efficient framework. Please contact us for supplementary physical or electrical features that can suit your needs.
特色
- General-Purpose IO
- Multi-voltage 1.8V / 3.3V switchable operation
- 25MHz, 75MHz, & 150MHz GPIO speed options
- Full-speed output enable
- Independent power sequencing
- Schmitt trigger receiver
- 60KΩ selectable pull-up or pull-down resistor
- 2KV HBM, 500V CDM, and 2KV IEC 61000-4-2 capable
- I2C/SMBUS Open Drain I/O
- Up to 5V tolerant
- Output enable
- Hysteresis input
- Power-on sequence independence
- Fail-safe
- External resistor support of 1KΩ - 50KΩ
- ESD protection of 2KV HBM, 500V CDM
- Also DDC, CEC and HPD compliant
- ANALOG
- 1.8V & 3.3V tolerant options
- ESD protection of 2KV HBM, 500V CDM
- Physical Features
- 55um x 81um cell size
- 8 metals, 5X2R
- 55um single inline wirebond pitch
优势
- Area-efficient
- Dynamic multi-voltage operation
- Drive strength options
- Customizable
- Pull-up / pull-down resistor options
- Feature-rich
- Robust
- I2C open-drain & analog cells
- Silicon proven
可交付内容
- GDS
- CDL netlist
- Verilog stub
- Verilog behavioral model
- LEF
- Liberty Timing Files
- IBIS (option)
- Electrical datasheet
- User guide and application notes
- Consulting and Support
应用
- 1.8V-3.3V GPIO, RGMII, 5V I2C/SMBUS, DDC, CEC, HPD, SD.
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