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A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell

The Certus TSMC 180 IO library is specifically tailored to address gaps in the native foundry IO offerings for this node. It features a 1.2-1.8V GPIO with selectable dual drive strengths and optional internal 105KΩ pull-up or pull-down resistor. ESD protection cells for IO and core supplies are constructed in an efficient 60um x 80um footprint. The analog suite includes 1.8V and 5V low-cap analog / RF cells, a 7.5V OTP programming cell, and an ultra-low leakage / low capacitance 20-36V HV analog cell using only baseline CMOS processing layers. The library is enriched with filler, corner, domain break, and secondary CDM cells to allow for flexible segment construction.

Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we consistently exceed the standard ESD targets of 2KV HBM and 500V CDM, but we also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).

Certus supports IO libraries across multiple TSMC nodes including 180nm, 130nm, 65nm, 40nm, 28nm, 22nm, and 16/12nm. Certus is particularly suited at providing custom variants in a cost-efficient framework. Please contact us for supplementary physical or electrical features that can suit your needs.

特色

GPIO:

1.2V-1.8V operation (IO & core)
Selectable 15pF | 30pF load support options at 50MHz
Schmitt trigger receiver
105KΩ selectable pull-up or pull-down resistor
ESD: 2KV HBM, 500V CDM
Silicon-proven

ANALOG

1.8V and 5V tolerant options
20-36V High-voltage, low leakage cell
Low capacitance / RF
Substrate isolation
2KV HBM, 500V CDM

OTP Programming Cell

7.5V tolerant supply gating cell
2KV HBM, 500V CDM

Physical Attributes

6-metal stack - 1MN_RDL
60um x 80um cell size
Flip-chip using client configurable pads

优势

Overdrive / underdrive options of 1.2V-1.8V (VDDIO, VDD)
Selectable drive strengths
Pull-up / pull-down resistor options
1.8V and 5V tolerant low-capacitance / RF analog cells
20-36V HV ultra-low leakage, low-capacitance analog cell
60um pitch flip-chip
Secondary CDM cells
Silicon proven

可交付内容

GDS
CDL netlist
Verilog stub
Verilog behavioral model
LEF
Liberty Timing Files
IBIS (optional)
Electrical datasheet
User guide and application notes
Consulting and Support

应用

LVCMOS GPIO, Analog, OTP, HV

Block Diagram of the A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell

A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell Block Diagam

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