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A 16nm/12nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO, 5V I2C open-drain, 5V OTP and 1.8V / 3.3V analog

A key attribute of the Certus 16nm & 12nm IO libraries is their ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation. The GPIO cell can be configured as input, output, open-source, or open-drain with an optional internal 50K ohm pull-up or pull-down resistor. Four selectable drive strengths are offered (25-235MHz @1.8V, 10pF) to optimize across SSO currents & power. The output driver exhibits 50Ω (±20%) termination across PVT to reduce reflections at higher operating frequencies. ESD protection for VDDIO, VREF, and core VDD is constructed in an aggressive footprint. A 5V I2C / SMBUS open-drain (fail-safe) cell, 5V OTP programming gate cell and 1.8V & 3.3V analog cells are also available. This library features protection break cells to allow for separate grounds while maintaining ESD robustness.

Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we consistently exceed the standard ESD targets of 2KV HBM and 500V CDM, but we also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).

Certus supports IO libraries across multiple TSMC nodes including 180nm, 130nm, 40nm, 28nm, 22nm, and 16/12nm. Certus is particularly suited at providing custom variants in a cost-efficient framework. Please contact us for supplementary physical or electrical features that can suit your needs.

特色

GPIO:

Multi-voltage 1.8V / 3.3V switchable operation
4 selectable drive strengths (25-235MHz @1.8V, 10pF)
Full-speed output enable
Independent power sequencing
50Ω (±20%) source termination across PVT
Schmitt trigger receiver
50KΩ selectable pull-up or pull-down resistor
30um cell pitch (flip-chip)
2KV HBM, 500V CDM; 2KV IEC 61000-4-2 capable
Silicon proven

I2C / SMBUS Open-Drain I/O:

Up to 5V external supply support
Hysteresis input
Power sequence independence
External resistor support of 1K-50K Ohm
Fail-safe
2KV HBM, 500V CDM; 2KV IEC 61000-4-2 capable
Also DDC, CEC and HPD compliant

ANALOG

1.8V & 3.3V tolerant options
2KV HBM, 500V CDM; 2KV IEC 61000-4-2 capable

Physical Attributes

30um x 50um cell size
8-metal or 10-metal stack
Flip-chip package support (client configurable pads)

优势

Area-efficient
Dynamic multi-voltage operation
Selectable drive strengths
Customizable
Pull-up / pull-down resistor options
Feature-rich
Robust
Open-drain & analog cells
30um flip-chip cell pitch
Silicon proven

可交付内容

GDS
CDL netlist
Verilog stub
Verilog behavioral model
LEF
Liberty Timing Files
IBIS (option)
Electrical datasheet
User guide and application notes
Consulting and Support

应用

RGMII, EMMC, SD, LVCMOS, GPIO, I2C, DDC, CEC, HPD, MIPI, and various other standards

Block Diagram of the A 16nm/12nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO, 5V I2C open-drain, 5V OTP and 1.8V / 3.3V analog

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