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Vesa dsc 1 2b frame buffer compression ip subsystem IP Listing

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VESA DSC 1.2b Encoder for Xilinx FPGAs

VESA Display Stream Compression (DSC) 1.2b compliant ; Supports all DSC 1.2b mandatory and optional encoding mechanisms ; Backward compatible to DSC v1.1 ; Configurable maximum display resolution ...

1
VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs

VESA Display Stream Compression (DSC) 1.2b compliant ; Supports all DSC 1.2b mandatory and optional encoding mechanisms ; Backward compatible to DSC v1.1 ; Configurable maximum display resolution ...

2
Ultra-Fast Baseline and Extended JPEG Encoder Core

This JPEG compression IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC ...

1 Testimonial
Masaitsu Nakajima, Head of Automotive Business Unit, Socionext

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DSC Encoder

Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has been also adopted into the VESA's eDP v1.4 ...

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